(1) Field of the Invention
The present invention relates to a method of fabricating capacitors of integrated circuits, and more particularly to the buried N+silicon-to-polysilicide capacitors with low voltage coefficient of capacitance(hereinafter referred as VCC) of high density ICs.
(2) Description of the Related Art
A mixed-mode circuit includes logic circuits and analog circuits. A capacitor is one of the most important devices in the mixed-mode circuit and the voltage coefficient of capacitance is a key parameter to determine the operation performance of a capacitor. For the actual application to the IC manufacture, the VCC value is generally demanded to be less than 100 ppm/V.
The definition of the voltage coefficient of capacitance is the partial derivative of capacitance relative to voltage per standard capacitance. Please refer to the following formula: ##EQU1##
For the early mixed-mode process, the VCC values of obtained capacitors are generally less than 50 ppm/V, and match the specification of IC manufacturers. However, in recent years, the cell amount of ICs has been enhanced significantly, and the packing densities of ICs have been increasing considerably. In order to achieve high packing density, the cell sizes of ICs cell must be shrunk. As the sizes of the capacitors become smaller, the capacitance values of the capacitors are decreasing and the VCC values are dramatically increasing, causing the performance problem.
FIG. 1 shows a cross-sectional view of a conventional buried N+silicon-to-polysilicide capacitor. The process steps are briefly described as follows: A silicon substrate 1 with field oxide isolations 2 is provided. A buried layer 5 is formed by doping N-type impurities into the substrate 1 as the bottom plate of the capacitor. A dielectric layer 6 is then formed by thermal oxidation for the capacitor, and then a polysilicon layer 7 and a polysilicide layer 8 are formed by the low pressure chemical vapor deposition (LPCVD) method in consequence. Finally the polysilicide layer 8 and the polysilicon layer 7 are partially etched in consequence, and then the top plate 9 of the capacitor is formed.
The wafer numbers 1-3 of FIG. 2a show the capacitors formed by the conventional process with plate size 100*100 .mu.m.sup.2 having VCC values between 132 and 334 ppm/V, all of which are much higher than the application standard value 100 ppm/V. The wafer numbers 1-3 of FIG. 2b show the capacitors formed by the conventional process with plate size 40*40 .mu.m.sup.2 having VCC values between 148 and 2538 ppm/V, which are also much higher than the application standard value 100 ppm/V.
The present invention discloses a new method to fabricate a buried N+silicon-to-polysilicide capacitor with low voltage coefficient of capacitance.